Reliability Analysis And Thermal Resistance Degradation Of High Power Devices In The Long-term Harsh Environment

With the power increase and volume decrease of power package device, the thermal density of which increases sharply, and the thermal dissipation problem becomes more and more serious. As the particularly important part named chip paste solder layer over the thermal dissipation channel, the soldering quality of which is the key to affecting the package device’s reliability.This paper based on a certain type of package device establishes a finite element analysis mode against to the problems of higher power(100W thermal power) in IGBT chip. And the finally structure of thermal dissipation system is determined to be a micro tube tunnel thermal dissipation by rationally analyzing the overall packaging device. The range of the convective heat transfer coefficient Nu is 576.9 to 8042.0, and the lower limiting value of average temperature Tm of the cooling is-45℃, which provides a theory foundation of the model simulation.According to the void standard MIL-STD-883 E and GJB548A-96, The effect of the variation of void size and position on the maximum temperature of chips and the maximum stress of solder layer is researched when some voids produce in solder layer. And the results show that, firstly, the solder layer corner voids affect the maximum temperature most and the maximum temperature difference could be as high as 34.112℃ compared with the normal solder layer; Secondly, with the increase of solder layer center and corner void area, the highest temperature of the chip are linear increased. The maximum equivalent stress of solder layer increases parabolic as the central area of the solder layer growth. However, with the growth of corner void area, the maximum equivalent stress of solder layer grows sharply, then smoothly and rapidly again at last.The fatigue life of the solder layer is predicted to be 6251 cycles and 5439 cycles under temperature cycle conditions based on Coffin-Manson method and energy density method respectively. And the results show that the life predicted by Coffin-Manson method keeps basically unchanged as the increase of void area when voids occur in the center of solder layer, but the life predicted by energy density method keeps decrease to1122 cycles. In addition, the predicted life of both two methods are decreasing and the minimum value is 1443 cycles predicted by Coffin-Manson method as increase of void size when the voids generate on the corner. Finally, we find that the energy density method which is not sensitive to mesh generation is more accurate.The crack growth rate, thermal resistance and thermal resistance degradation rates of solder layer will increase when voids generated in welding layer, and the maximum value of crack growth rate is 2.710×10-4 mm/cycle turned up at the corner voids, while the maximum permissible value of resistance, 0.0265 K/W, appears to center voids, and the corresponding thermal resistance degradation rate is 1.12×10-6 K/(W?cycle).