Design Of Color Image Compression Algorithm-hardening In High Level Language

With the development of FPGA, advanced hardware platforms are equipped with thefeatures of high speed, parallelism, rapid exploitation of digital system’s prototype andoptimisition. Meanwhile, digital image compression technology is widely used ininformation age and JPEG image compression algorithm is the most classical one.Theadvantages of FPGA with high speed, parallism and optimization are taken in theimplementation of image compression algorithm in hardware platform.This thesis introduces the history of algorithm-hardening development and makes acomparison of traditional algorithm-hardening method and the latest method based onC-to-HDL technology. Taking development method and efficiency and other factors intoconsideration, this thesis proposes an algorithm-hardening approach based on high levellanguage Handel-C and gives a detailed introduction to its development flow.On the basis of analysis and research on the fundamentals of JPEG compressionalgorithm, this thesis gives a plan of implementing JPEG compression algorithm inHandel-C and realize each functional component. Handel-C’s priority of supportinghardware parallelism is made good use of in the procedure of implementing JPEGalgorithm-hardening by adding parallelism to each functional component of thecompression algorithm: the DCT component and the quantification component areparallelized by2times with the zigzag component parallelized by4times, resulting in ahigher execution efficiency. High-definition color images with a resolution of1920*1080are used in the verification of compression algorithm-hardening system withAltera’s DE2-115board as test platform.The verification results show that the compression system is good in performancewith the result images’ compression ratio higher than20and PSNR higher than40dB.This thesis’s work might be helpful and instructive to the later research on and useof the approach of algorithm-hardening in Handel-C.