Research And Asic Implementation Of The H264&avs Hd Video Decode Chip

AVS is a video coding standard, which developed by China herself, H.264/AVC is an international video coding standard, which has high performance. Compared with the MPEG-X and H.26X compressed video standards that were establish before, the H.264 and AVS standard can offer better video picture quality and compressing rate.Research in the video decoder, which can support both AVS and H.264, has big significance.Because it can improve the function of the chip and it also has far meaning for people who will research in video decoder, which can support two or more than two video coding standards.Though AVS and H.264 have big differences in algorithms, they also have common grounds,so this design reuse some modules in using the common grounds,in order to reduce the cost of hardware and enhance it's market competition.Use PCI bus to transfer bitstream and debug the whole system in this designer.AVS and H.264 decoder need extra high bandwidth requirement because of AVS & H.264 standard's some new features, such as: multi- reference pictures, variable block size, and four\six taps interpolation filter. Consider bandwidth requirement and system cost, choose DDR SDRAM as extern memory in this video decoder. This paper will emphasis on introducing PCI DMA controller design,reference picture's format in DDR SDRAM and reference block read after introducing the whole system design.In design method, we use the Top-down design method in whole design. In order to verify decoding algorithms and provide test vectors for every module, we designed C model first, then do the simulation in every design step. We also analyzing the circles of parsing process for AVS and H.264 video streams. At last, we do the FPGA verification and ASIC synthesis.The decoder can decode standard-definition video in FPGA and can decoder high-definition video in real time if use 0.18μm CMOS.