64-bit MIPS CPU's Module Design & FPGA Verification

With the development of IC design and technology, SOC has been wildly applied in information terminal such as PDA, STB and mobile etc.. It has many advantages. Not only can it decrease the circuit scale, but also it can reduce the cost, improve the stability and lower the power. The SOC is the tendency of IC in the future development. As the core of SOC, microprocessor is the essential part of it. The CPU's performance directly determines the SOC's performance.Comparing with the advanced international technique, the research and development work in this field falls behind in China and it directly affects the development of China's information industry. For keeping up with the advanced foreign technique, filling the blank in this field of our country to shake off being bounded by foreign company, many research units devote their efforts to the development of it. For several years of exploring, some self-intellectual property rights processor chips have stepped into the market after their designing and verification. The history of no cpu has finished, and we are stepping to target of designing the more performance microprocessor. China has ended the "none chips" history and aimed at designing higher performance processor.The VEGA CPU is high performance 64-bit RISC processor designed by Arkmicro co. ltd. with their own technique and research. This cpu is based on MIPS ISA architecture with five stage pipeline and virtual memory management technique used in high performance processor. The design process is up-to-down and VEGA is divided into several functional modules such as instruction fetch, decode, ALU, MMU, pipeline control and cache control etc. It enables our designing according to it's function and timing requirement.The paper first introduce the characteristics of MIPS processor especially MIPS ISA and it's five stage pipeline to give us a direct impression of VEGA. Based on this, the paper put forward VEGA's structure divisions and module functions. As the processor has virtual memory management, the main part of paper introduces the memory management system, and puts the MMU especially two internal TLB as emphases and explains the design method of pipeline processor. It can't be proved the designing is right after logic design and simulation. It still needs to be vivificated in real hardware platform. As another emphasis of the paper, it introduces the FPGA configuration units used in VEGA and FPGA design flow. The FPGA platform of VEGA is a complete computer system, we did the onlinedebug to correct the design errors with Xilinx Chipscope.After module design and final FPGA verification, VEGA finished it's logic design and bottom flow with synthesis and place and route. The VEGA reaches to 120MHz with adoption of 0.13 technological process. Windows-CE and Linux embedded operation system can run on the VEGA platform. The design meets the expected requiments.