Design And Implementation Of Computer Screen Recorder Based On Fpga And Arm

With the prevalence of computers, there are more and more situations where we need to record computer's screen content. Meanwhile, the resolution of display monitor is increasing so rapidly that the resolution of images to be recorded is becoming larger and larger. Therefore, it is increasingly important to develop an equipment to record the computer's screen information. In this thesis, the image compression algorithm based on DWT is firstly researched, and then a computer screen recorder is developed based on the algorithm.The theory of Discrete Wavelet Transform (DWT) is presented in 1970s. The coding efficiency and the quality of reconstructed image using DWT are better than those of using traditional DCT. Spatial Combinative Lifting Algorithm (SCLA) is proposed under the scheme of lifting. It requires less amount of multiplication in terms of combining the horizontal and vertical transforms of 2D-DWT. As it is suitable for hardware implementation, SCLA is adopted to achieve better and faster coding in our computer screen recorder.Tree-based coding algorithm is a family of coding methods for wavelet coefficients. In this thesis, some classical tree-based compression algorithms are discussed firstly and then a trade-off is made between implementation complexity and compression performance, according to those algorithms'implementation characteristics. An algorithm called SLC is proposed and the algorithm can achieve relatively better performance and decrease the implementation complexity .In this thesis, two image compression platforms are built. One is used to verify the proposed algorithm and the other is the computer screen recorder based on an architechture of FPGA+ARM. The recorder can record computer screen with SXGA (1280×1024×24bits) resolution in real time. The compression performance is similar to JPEG2000 and far better than JPEG.