The Design And Implementation Of Vector Integer Mac Unit Of Ft-matrix Dsp

DSP is the key component of the data operation of the wireless communication. In the fourth wireless communication of the future, speech and data processing rate of personal users will raise substantially. In the process of audio and video, it involves a great deal of data operation, such as discrete cosine transform and inverse transformation, fast fourier transform, encode/decode and so on. It needs to complete a hundread million or even hundread billion operations per second. Multiply accumulate is the major operation of the data processing. It is very important for us to research a high performance MAC (Multiply Accumulate) unit for the SDR (Software Definition Radio) DSP of fourth wireless communication.FT-Matrix DSP, which is researched by us independently, is a 32-bit high performance Digital Signal Processing. We own the intellectual property rights of it. Its architecture is VLIW and it can issue 10 instructions in a cycle. It also has a SPU (Scalar Procseeor Unit) and a VPU (Vector Processor Unit). The VPU is composed of 16 isomorphic PEs. We use it in the high density arithmetic. In this paper, we raise a new thought about the design of the VIMAC (Vector Integer MAC) unit, and we do a good research in requirement analysis, design about the VIMAC. We also do a good job on the verification and synthesis about the SIMAC (Scalar Integer MAC) unit of FT-Matrix DSP.In this dissertation, we research on the key arithmetic of 3GPP, complete the design of the instruction set of the VIMAC unit. The VIMAC unit of the FT-Matrix DSP can execute a 16bit×16bit+40bit fix-point vector instruction with the 16 SIMAC work simultaneously, which also support 8bit×8bit+20bit fix-point vector operation. In order to raise the processing rate of the add operation, we design a multifunctional pipeline which support the execution of VIMAC instructions and fast VADD (Vector ADD) instructions in the VIMAC unit. In the design of the SIMAC, we use the modified Booth algorithm to reduce the number of the partial product, add the partial product by the Wallace tree which composes of the compressor. In order to decrease the area of the SIMAC unit, we carve up the Wallace tree by using triangle partition, which also decrease the power and critical path delay of the SIMAC unit at a certain extent.In the implement of the 32bit×32bit multiply, we resuse the 40bit adders in the third stage of the pipeline which descreases the cost of the hardware. In order to deal with the multi-kind of saturation, we design the dynamic saturation logic to detect saturation and modify the final value.We also research on the multiply-accumulation fused technology and apply for a patent, which will be used in the next generation of the SIMAC unit.Based on the simulations from both module level and system level by using the tool of NC Verilog, the paper discusses the verification of the SIMAC unit, raises the test way, develops the efficient, self-contained testbench, constructs the verification model. All of them show the design is correct.Then, we do a synthesis of the SIMAC unit, the result show that the frequency of the unit is 500MHz, the area is 48345.6μm~2 and the dynamic power is 12.52 mw, all of which reach the goal. At the end of this paper, we compare the performances of the SIMC unit designed by this paper with the conventional SIMC unit, which show that the performance of the fisrt SIMAC unit is better than the last SIMC unit in the dynamic power and the critical path delay, and the area descreases about 3500μm~2.