High Performance Low Cost Float-point Multiply-add Fused Unit Design And Its Creditability Validation

The performance of scientific computing has played the role of bottleneck of development of many industries. Godson-T which locates itself of the high scientific computing parallel computing chip solutions in the future as, naturally, has a high performance requirement for floating-point calculations.As a key of high performance of scientific computing, Floating-point MAC directly influences the peak performance of floating-point of chip. In addition, the location of part of many-core CPU makes the area of FMAC became very sensitive parameters. Cause that with the same technology, only the smaller area made more mini-cores on one chip. Finally, as a commercial level IC project, the correctness verification of the FMAC becomes the most critical.Facing to this strict request of design, by the re-proposing the fastest present LANG&BURRANG complex algorithm method which" multiply-addition-normalization-rounding" and based on the improvement for the optimization of area and delay of some local structure, and the implementation of the original testing and verification system, and a high performance and area efficiently design is achieved. In 65nm TSMC 1GHZ of frequency and 0.12 mm2 of area is achieved.the traditional Wallace tree occupy nearly 70% of area of floating-point MAC, so through deeply researched and analyzed the organization method of Wallace tree, and the resource redundant of the traditional organization of Wallace tree was found. And with programming method of automatic generation of RTL code is overcome redundant free Wallace tree structure and trivial asymmetry of organization construction complexity and the engineering failure by the complexity. Finally completed 4:2 Wallace trees which is redundancy free and bug free, This work reduces e 48% of area of Wallace tree, reduce the 30% of area of FMAC.in the verification of FMAC, after going through the popular program of float-point unit, we propose a verification system for complex digital IC project, in which there is much method like popular verification means in Industry, and there also are some methods of original means. The core sense of this verification system is Classification or extraction in many angles and verify targeted once by once.