Research On Reliability Of On-chip Router And Its Fault-tolerant Design

With the rapid development of semiconductor technology, more and more IP cores will be integrated on one single chip. But the chip bus based SoC design encounters many problems, such as hard to synchronize the global clock, address space is limited, cannot support multi-node paralle communications, as well as the system expansion is not flexible enough. All these problems seriously restricted the improvement of the system performance. Network on chip (NoC) technology introduced computer network technology into SoC design field, completely solved the above problems from architecture, gradually developed into a new communication structure besides the chip bus, and became a new research hotspot in the field. Most of the current researches for NoC focus on optimizing the performance of the topology, routers and routing algorithm. But as the system complexity increases, reliability has become a problem must be studied. Routers are responsible for on-chip communications, so the reliability research for them is more important.This paper described the design of the composition and transport protocol of the on-chip router based on the 2D mesh structure, and classified the faults in the on-chip router as well. Combining the characteristics of the on-chip router, and routing technology commonly used in Parallel computer and Fault-tolerant technology used in distributed systems, a reliability design of a reconfigurable on-chip router based on a 2D mesh topology has been proposed. A backup path mechanism is assumed to implement the fault-tolerant design of routing nodes, network interfaces, links, etc. The system can still communicate well even if all of the routing nodes fail. A great improvement of reliability is obtained with low cost of hardware overheads. Furthermore, analyzed the fault-tolerant routing algorithm for NoC, and a routing algorithm can avoid deadlock used in this paper. Using gpNoCsim simulator which written by Java to modeling and simulate the design, analyzed the results, evaluated the fault-tolerance design improving the reliability of the on-chip router.