Study On The Frame Rate Up Conversion Technology Based On FPGA

With the fast development of digital TV and the big screen display equipment,shadow, shaking, motion blur and some other pheromone with the LCD panels havebecome a big problem.In order to solve the problem mentioned above, on one hand,researchers reduce the response time of liquid crystal molecules panel and on the otherhand, they reduce the time on maintaining the liquid crystal molecules through theimprovement with LCD panel refresh frequency.According to the physical properties of liquid crystal molecules, the response timecould not be reduced without limitation; therefore, many experts and scholars try toimprove the refresh frequency of LCD panel. The first kind of frame rate up conversion(FRUC) method is one of these approaches, which doesn’t consider object movementsof frame copy, average and interpolation. However, these algorithms have variousdefects because of too simple. The second is based on ascension and motioncompensation (ME/MC), which includes the motion objects and effectively solves theproblem. The fast and accurate motion estimation is the basement to get high qualityframe of interpolation.This paper mainly researches a FRUC algorithm for the hardware realizationcircuit. It mainly studies the hardware complement circuit with FRUC algorithm whichis based on C language and Matlab simulation. Besides, this paper makes a compromisebetween the hardware realization characteristics and the requirements of visualperformance which would be able to meet the requirement of video signal real-timeprocessing, and don’t reduce subjective visual effect. The paper mainly works are asfollows:①The real-time processing frame structure of the succession of the water level ispresented; a frame division within the image bands, strip macro block data update areintroduced;②The motion estimation based on SAD matching criterion is realized; the theoryprinciple, timing diagram, structural design and simulation results have been analysed;③The original image video frame structure, the division of bands, and data updatewith DRR in SRAM module are researched;④The data buffer unit of SRAM module with motion estimator is realized; theprinciple, timing diagram, structural design and simulation results have been analysed; ⑤The motion estimator supportted SAD and VOD matching criterion andmultiplexing most hardware resource is realized; the principle, timing diagram,structural design and simulation results have been analysed;⑥Improved design and original design on resources consumption is compared; thehardware advantages with the improved design based on resource consumption analysisis presented;Through the above work, a bilateral ME structure is realized, which has high rateof data reuse, fast calculation, and low hardware comsumption.It has been verifiedthrough simulate results.