Research Of Fast Discrete Hilbert Transform Computation In Helical Cone Beam CT Reconstruction

The theory of exact helical cone beam CT (CBCT) reconstruction has been proposedless than a decade. This theory has broad prospects. CBCT algorithms can be usedto locate tumors accurately in radiation therapy. Real time computation is required inradiation therapy to short the waiting time of patients. Some fast calculation methods areproposed, but real time computation of CBCT algorithms is still not efectively resolved.Discrete Hilbert transform (DHT) is an important method in filtering of CBCT algorithms.A lot of projection data needs to be processed in filtering. Hundred of thousands of DHTswith large points need to be calculated in filter normally. The amount of data becomesmore and more along with the improvement of pixels in detector and projection numbers.More image data and the real time requirement needs fast computation of DHT. In fact,DHT costs a large part of time in image reconstruction algorithms. The computation timeof CBCT algorithms is closely related to the performance of DHT.The dissertation discusses foreign and domestic research status of DHT, and re-searches fast DHT computation from the time domain, the frequency domain, hardwaredesign and software design. Proposed DHT modules are tested in sloping filter testbench.The major works of the dissertation are listed as following:1. DHT can be processed by FFT, and FFT requires the sample points N must be inpowers of two. Sequences with sample points no powers of two need to pad zero to fit therequirement of FFT. Zero padding brings a lot of redundant computation. In order to solvethis problem, A parallel DHT method and its implementation is proposed, which is usedto compute sequence with sample points N divisible by four. Four outputs are calculatedsimultaneously in the parallel method. Comparing to the matrix formulation of DHT, theparallel method reduces N28additions and N2multiplications. According to the parallelmethod, a single channel and a4-channel pipelined DHT processors are implementedrespectively. The single channel processor includes a ping pong cyclic shifter to ofercontinuous data processing. In the4-channel processor, odd and even index inputs aresaved in two cyclic shifters separately;2. When computing DHT in memory based structure, there is at least one processingelement in the circuit. A configurable memory-based DHT processor is presented. Thisprocessor adopts radix-2algorithm with decimation in frequency. The processor supports FFT, IFFT and DHT. Memory accessing in IFFT uses bit-reversed addressing to avoiddata permutation. The processing element (PE) has four configured modes to fast computediferent stages in DHT SFG. Euler formula is used to decrease the memory space ofrotation factors;3. Pipelined structure is suitable for continuous data stream, and pipeline technol-ogy is important in real-time signal processing. The clock latency is closely related tohardware resource costs. A novel repartitioned method of DHT SFG based on radix-2al-gorithm is proposed. DIF FFT and DIT IFFT are cascaded in DHT SFG. We combine thelast FFT stage, the frequency DHT, the first IFFT stage and twiddle factors multiplicationin the second IFFT stage into one stage, and the rest stages of IFFT are repartitioned toDIF decomposition. Two stages are decrease, and no bit-reversed permutation in the SFG.This method simplifies the design of processing elements (PE) and reduces hardware re-source. The pipelined DHT circuit includes five types PEs. These PEs can be cascadedserially to calculate DHT with any length;4. A DHT software structure based on SIMD technology is proposed to reach the fullperformance of general processor. A DHT software library is designed, which supportsFFT, IFFT and DHT. Split radix and mixed radix algorithm are adopted in this library.Bit-reversed permutation and matrix transposition are combined into one step to reducememory accessing and promote DHT library performance.A testbench including Katsevich algorithm is designed. This testbench is used tomeasure the performance of sloping filter in Katsevich algorithm by using proposed DHTcircuit structures, and verify the function of DHT module.