Research On Hardware Implementation Method Of Aes Cryptogram

In the modern society, the informatization and networking bring about convenience to the life of people, but the hidden danger for information security is increasingly obvious. Encryption technology is an effective method to solve this problem. NIST officially approved Rijndael of the Advanced encryption standard(AES) on November 26th 2001.With the fast encryption speed and the high level of security, AES cryptographic algorithm has become the actual encryption standard of various forms of electronic data. At present, the encryption technology for AES cryptographic algorithm has become a hotspot. This paper puts forward a kind of low-cost implementation method of AES cryptographic algorithm. This method of hardware implementation uses the FPGA device to implement this specific design scheme, and the AES encryption chip based on FPGA is designed.Firstly, this paper puts forward the system architecture of AES cryptographic system, which adopts non-pipeline structure implement two working mode: ECB non- feedback mode and CBC feedback mode. It can improve the system configurability and meet the needs of practical work. In addition, in the process of algorithm implementation, through the configurable S-box and optimized invmixcolumns transform, the direct decryption algorithm structure partly eliminates the difference between encryption and decryption hardware structure, and then the design target to reduce the hardware resources is achieved.Secondly, the framework for the system architecture is modeled by Verilog HDL. According to the test date provided by relevant documents, this design uses ModelSim tool to simulate and verify each module and the whole system module, and uses Altera QuartusII tool to complete the system synthesis. The result shows that the AES cryptographic system reaches the expected low-cost goal, which reduces the hardware resources and balances the scale and speed on the basis of meeting the encryption and decryption speed.Finally, the configuration file which is generated after compilation and synthesis is downloaded to EP1C12Q240C8 Cyclone device, thus the FPGA configuration process is completed, and then the design process of the AES cryptographic system is fully implemented, and the AES encryption chip based on FPGA is designed.