Design And Implemention Of Hybrid Encryption And Decryption Engine Based On FPGA

In the communication environment,cryptographic algorithm is an effective means of ensuring data security.According to fast data processing and easy standardization,the symmetric cryptographic algorithms represented by AES and 3DES are widely used.But its single key processing method has potential leakage risk in transmission.With the rapid development of information network technology,computers need to provide more security functions for data encryption and decryption.In hardware implementation,the traditional way of applying multiple functional cryptographic algorithms to hardware simultaneously generates large system power consumption and logic resource consumption,which is not conductive to practical applications.Based on the above problems,this paper designs a high flexibility,low power consumption and multi-function hybrid encryption and decryption engine based on ARM core ZYNQ-7000 series FPGA.The engine supports data encryption and decryption,key encryption and decryption and data authentication.The dynamic reconfigurable platform for multi-algorithm system resource problems is designed,which implements dynamic switching of multiple hybrid encryption and decryption functions.The main contents are as follows:Firstly,the multiple encryption and decryption functions implementation scheme of the hybrid encryption and decryption engine is determined.The algorithm modules of each function are designed separately,and the function test and hardware implementation performance analysis are completed.For data encryption and decryption,two hybrid encryption and decryption methods of RSA-AES and RSA-3DES are designed and implemented respectively,which can be selected by the host computer.For data integrity verification,the basic iteration structure and the full pipeline structure of MD5 algorithm are designed respectively based on the size of data processing,and the data processing speed of the two is compared and analyzed.In order to improve the security of message digest,this paper designs the encryption and decryption implementation of RSA-MD5.Secondly,the dynamic reconfigurable function implementation scheme of the hybrid encryption and decryption engine is designed.Based on the characteristics of RSA-AES and RSA-3DES hybrid encryption and decryption,the cryptographic algorithm reconfigurable module is determined.According to the characteristics of ZYNQ-7000 series FPGA,the software design of the dynamic reconfigurable platform and processing system of the programmable logic area is completed,and the dynamic switching of the two hybrid encryption and decryption functions is realized under the normal operation of the system.Finally,the system of the hybrid encryption and decryption engine is completed,and the data transmission and algorithm reconfiguration by the host computer and the FPGA are realized through the serial communication.Based on implementation of each encryption and decryption function,the control relationship between the encryption and decryption modules is established,and the reconfigurable area on the FPGA is constrained to complete the overall layout.The LABVIEW software is used to design the host computer.On the basis of the overall system function simulation test,the data transmission test of the host computer is completed.According to the two aspects of resource consumption and reconstruction speed,the performance analysis and comparison proves that the hybrid encryption and decryption engine based on dynamic reconfigurable technology designed in this paper not only implements multi-function encryption and decryption,but also improves the system flexibility and reduces the logical resources consumption.