An SER Estimation-based Automatic Logic Synthesis Method For FPGAs And Verification

SRAM-based field-programmable gate array (SFPGA) has been very popular inmany applications, including embedded systems, industry and spacecraft, storagesystems, cryptography, network, and so on. This is mainly due to the fact thatSFPGAs can offer high performance, low non-recurring-engineering (NRE) cost,suitability for implementation of large circuits and fast time-to-market. As the featuresize of FPGA shrinks to nanometers, it’s much likely that lower energy particles cancause an SEU. This makes FPGAs more vulnerable to soft errors and limits theFPGAs’ widespread application. Thus, how to improve the reliability against softerrors becomes increasingly an important concern in SFPGAs. On the other hand, withthe rising increasing of FPGA design scale and complexity, the reliability of designdirectly affects the reliability of products. So it’s really necessary to do a full andeffectively validation on the FPGA design. The thesis mainly includes:1. The sensitivity of the global interconnect in FPGA is very important to thereliability of the circuit. This paper proposes a soft-error-rate-based logic synthesismethod to improve the fault-tolerance of the global interconnect, and improve theFPGA reliability. The method includes three parts:a) Clustering is the key step in hierarchical FPGA CAD flow, and the result ofclustering directly decides the circuit’s performance. According to the fact that faultrate at a global interconnect is proportional to the average sensitivity of SRAMs alongits routing. We add the encapsulate interconnects with high sensitivities inside CLBsas the clustering object;b) Due to accurate NER can only be obtained after placement and routing, weestimate NER in the clustering phase. We found that a net’s NER is proportional to itslength from the analysis of the FPGA’s architecture. Using the existing ISPL metricwe can estimate node error rate;c) Combining error propagation probability and estimated node error rate byusing the existing ISPL metric, we can get the estimated SER during clustering andincorporate it as a reliability factor into the clustering guidance criterion successfully.Hence the method reduces the number of the global interconnect with the high SERwhich leads to soft errors mitigation.2. Make use of the following steps: encoding rules checking, simulation-based verification, equivalence checking and static timing analysis to verify3FPGA design.We collect and analysis common errors.