Research And Implementation Of Partition Method Based Multi-FPGA

With the increasingly fierce competition in the IC companies,the focus has not only been limited to the design,but verification has gradually become a key factor affecting project development.Compared with the common verification method,such as software simulation technology,prototype verification technology based multi-FPGA has received more and more attention from verification team due to its advantages of iterative erasability and realistic hardware behaviour.This thesis,which is based on the idea of multi-FPGA verification,takes the example of Long Term Evolution chip as the principal line.And the paper focus on the logic partition method of multi-FPGA,including interconnection of multi-FPGA design,data transmission of multi-FPGA design,clock manager of FPGAs,building and functional test of FPGA prototype verification system.Firstly,the necessity that multi-FPGA prototype system needs logic partition has been expounded.And we discuss key issues of multi-FPGA prototype verification system: insufficiency of FPGA ports;errors of data transmission between FPGAs;clock synchronization management of multi-FPGA.New FPGA port architecture with ISERDES and OSERDES is proposed.With the help of the ISERDES and OSERDES,we can decrease the number of FPGA ports that is used to transmit signals down to 1/30 of original amount by adjusting frequency of serial signal and utilizing Ring Bus.New method for data transmission between FPGAs is presented.After the logic partition,this method guarantees the correction of data when they transmit between FPGAs by locking HREADY signal and extending HRESP signal.As a significant part of clock management,the asynchronous clock domain is studied.We can ensure different FPGA has a synchronous clock by using only one single clock and same MMCM?frequency multiplier for every FPGA.With regard to the issue of semi-stable state caused by reset signal after the logic partition of prototype system,we resolve it by using the circuit called Asynchronous Reset Synchronous Release.Finally,we discuss the setup of FPGA verification system platform from software and hardware,and the function of design that this paper proposed has been tested on the platform.The results show that: the function of multi-FPGA prototype verification platform is correct;the performance of interface module is satisfied;data transmission between FPGAs is correct;the method of clock management is effective and reasonable;semi-stable state of reset signal is disapper.The study of this thesis is innovative and reliable.