Analysis Of MIMO Detection Algorithm And Its FPGA Implementation

Due to the dramatic increase in the number of mobile communication users and the rapid development of broadband multimedia services, the demand for transmission rate and performance of mobile communication system becomes increasingly high, and extensive research has been conducted for this problem. As the growing tension of spectrum resources, Multiple Input and Multiple Output (MIMO) is recognized as the technology trends of wireless communication because of its ability to substantially increase the spectral efficiency. Among the various MIMO architectures, V-BLAST is a widely used multiplexing strategy with demonstrated capacity gain.This paper firstly introduces some classical MIMO detection algorithms under V-BLAST architecture, including traditional Golden algorithm and secondary algorithm based on Greville decomposition, compares their performance and complexity. Then it gives detailed analysis for fast ordering V-BLAST detection algorithm based on QR decomposition. This algorithm avoids the iteration for pseudo inverse which is necessary for traditional detection algorithms by a new ordering scheme, and realizes the same performance as Golden algorithm while decreasing its complexity greatly. This algorithm has been utilized in the wireless communication demo system developed by author's R&D team whose peak transmission rate reaches 1Gbps.The author took charge in the hardware implementation of MIMO detection algorithm in Gbps system. The main contribution can be divided into 2 parts, which are:1. System DesignAccording to the target of system design, define the system parameters for wireless interface; propose the overall hardware framework for receiver and design the protocol for the interfaces of MIMO detection module.2. Algorithm ImplementationAn effective and resource-saving FPGA architecture for this algorithm is proposed, including logic implementation, pipeline design, and fixed point programming. A novel method of LUT division design, "Multi-LUTs" strategy, is proposed to increase the performance of LUT divider. MATLAB simulation and hardware data are presented to validate the architecture, which achieves fixed and high throughput (1Gbps as peak rate) in real-time system.