| With the need for packet processing in high throughput networks, and the higher expense for high performance network processor, low cost programmable Network Processors on FPGAs are gaining attention. We utilize a hash function, small-size parallel CAMs, and an external RAM to implement a high performance 35 Gbps network processor to handle 524,288 flows. FPGAs are chosen to realize reconfigurable network processors for executing field upgrade. In this thesis, a hash function is proposed and implemented to analyze and route incoming packets to specific CAM architectures at high speed with low overhead. To match incoming packets with pre-stored flows, a parallel structure of CAMs is proposed to meet the high speed requirements. In order to provide a low cost and low power consuming solution, an external RAM is used instead of large-size expensive CAMs to store a large amount of information on flows at a fraction of the cost compared to the CAM. |
