An ultra low power 10 Gbps IC output driver with programmable pre-emphasis

This thesis describes a new topology and implementation of a 10 Gbps LVDS (low voltage differential signaling) voltage mode output driver designed for high speed data transfer applications. Using a positive feedback technique, the driver achieves ultra low power operation while maintaining the proper internal chip impedance required for matching the line impedance. As a result, signal reflection is minimized and good signal integrity is achieved. The driver, which consists of a pre-driver and an output stage, consumes a total of 15.63 mW at-speed power. In measurements, the driver, which is part of an equalizer chip, achieves peak to peak jitter of 11 psec at 10 Gbps and return loss performance less than -15 dB. It provides a single ended output swing of 400 mV and a common mode voltage of 1.25 V which are compliant with LVDS standards.;Also as enhancement to the first driver, this work describes a novel topology and implementation of a second 10 Gbps transmit voltage mode driver with pre-emphasis designed for driving lossy transmission lines at high data rates. Using a signal conditioning technique in the pre-driver and a positive feedback technique in the output stage, the driver achieves programmable pre-emphasis capability at very low power consumption. In measurements, the driver can reliably transmit a 10 Gbps signal through a lossy 14 inch FR4 stripline. It achieves a peak to peak jitter of 15psec, a differential eye opening amplitude of 200mV, and a return loss performance of -15dB. The proposed topology consumes less than half the power of current mode logic (CML) based topologies. It consumes 27mW at-speed power which includes both the output stage and the pre-driver.;Both drivers were designed in two separate high frequency equalizer test chips. They were fabricated in a standard National Semiconductor 2.5V/1.2V SiGe BiCMOS technology with 100 GHz peak ft, and packaged in commercial leadless lead frame packages, LLP.