B3g-tdd In The Downlink Mimo Detection Algorithm And Its Implementation Technology

Multiple-Input Multiple-Output (MIMO) technology is a major breakthrough in the field of smart antenna in wireless mobile communication. Without increasing the bandwidth, this technique can increase the capacity of communication systems and the spectrum efficiency several times than ever before, which is the key technology in next generation mobile communication systems.Nowadays, mobile communication is on its high-speed development period on a global scale. The research of China's beyond third-generation (B3G) mobile communication has been officially listed into 863 projects, and initiated the FuTURE project. University of Electronic Science and Technology of China is responsible for the downlink design of B3G TDD mode and now it has been the second phase of the project, the key point of which is to do research on the FPGA (Field Programmable Gate Array)implementation, based on the framework of MIMO-OFDM, and the transmission speed is up to 100Mbps.This paper does some research on the MIMO detection algorithm and its implementation of B3G TDD downlink. Based on the existed algorithms and the ideas of maximum likelihood estimation and sphere decoding, the paper proposes a maximum likelihood detection algorithm based on MIMO detection point, and a simplified algorithm is presented, which is then implemented based on FPGA.This paper first analyzes the characteristics of the known MIMO detection algorithms. Some of the algorithms are simple to be implemented but the detection performances are poor. Some have superior detection performance but are too difficult to be implemented. This paper combines the ideas of maximum likelihood estimation and sphere decoding, and then proposes a maximum likelihood detection algorithm based on MIMO detection point. This algorithm improves the detection performance significantly and its implementation is relatively simple. In the next, the proposed algorithm is simplified according to the features of this algorithm and the actual situation of this project, which greatly reduces the implementation complexity of this algorithm.This paper also does some research on the FPGA implementation of this algorithm. An overall design program is proposed, and then detailed illustrations of the FPGA design for every function module are given. Finally, the summary of the paper is presented and the work which should be carried out in the next step and the future research direction are clearly pointed out.