Research On Logic Emulation System Based On Multi-fpga System

With the expansion of the ASIC systems scale and semiconductor process development, research about multi-FPGA system as logic emulation of large-scale ASIC is gradually increasing. The logic emulation system based on single FPGA chip has insufficient capacity of logic resources and pin constraints, but Multi-FPGA system solves the problems. And because it's features that reprogramming and parallel processing, it makes the multi-FPGA logic emulation system currently designed into the mainstream ASIC verification technology. Multi-FPGA system is the large-scale systems that composed of a few pieces of chips and even dozens of FPGA chips in accordance with the certain topology. Through the analysis and comparison of the three programs of the realization of logic simulation, determined the need for multi-FPGA system implementation and feasibility. Then the key technologies for its implementation were discussed.Multi-FPGA system Implementation, focusing on FPGA chip interconnect their way (i.e. topology) were analyzed; In addition, when the large-scale ASIC's logic is mapping to multi-FPGA system, it needs to be logically segmented to successfully convert ASIC system to multi-FPGA. This paper summarizes that a number of available algorithms currently are improved algorithm based on the KL algorithm and FM algorithm, so the basic principles of the FM algorithm and the KL algorithm are introduced. Multi-FPGA systems another key technology is the system global clock synchronization. In this article, we proposed current clock synchronization program includes: clock tree scheme, the clock transfer scheme, he program based on the DLL components of FPGA chip and a hybrid of several programs. The clock synchronization is analyzed. Another key technology for multi-FPGA system, namely, configuration, this paper introduced a new configuration method about the Xilinx Company's FPGA chips. CPLD controlled the simple timing, with the PLATFORM FLASH PROM XCF32P partition as the configuration data storage, 4 FPGA chips in parallel configuration modes to complete its configuration. This program is fast and convenient.After analyzing the key technology of the multi-FPGA system, this article describes our multi-FPGA system design. The system is composed of four Xilinx Inc. VIRTEX series XCV200 FPGA chips, by improved MESH topology, using several clock synchronization programs and the above-mentioned configuration. We design the schematic and PCB. After analysts the simple performance of the system, we summarizes the advantages and disadvantages of this design.