Research On Timing Recovery Of Communication System

Timing recovery plays an important role in the receiver design of wireless communication system. It affects the sampling frequency requirements of the analog-to-digital converter (ADC) for incoming signals. However, for high data-rate applications e.g. ultra-wideband (UWB) system, the ADC circuits need to work at high sampling frequencies, which leads to significantly increased power consumption. Among the various timing recovery methods used in digital communication receiver design, popular algorithms based on polyphase filter-bank and interpolation are given. Unfortunately, these two methods are only practical when ADC sampling rate is high enough to reconstruct the signal, which means that the sampling rate should be at least the Nyquist rate or even higher.One possible approach is to let the ADC circuits sample at the symbol rate by using a multiple-clock generator. The generator provides several clock running at the symbol rate, each of them has equally spaced timing phase. By utilizing the timing recovery loop proposed, the optimal clock for ADC sampling can be chosen. However, the performance in this case is relevant to the number of clock phases. Insufficient number of clocks may result in large performance degradation. To decrease the number of clock phases, the idea using adaptive interpolation is proposed for Gigabit Ethernet with pulse amplitude modulation (PAM). In this paper, we propose a symbol-rate timing recovery approach for UWB system based on QPSK modulation. The adaptive interpolator using LMS algorithm is applied to decrease residual timing error.