A Design Of Symbol Timing Recovery In QAM Demodulation Chip

At present, QAM modulation and demodulation are adopted in cable DTV system, which is an asynchronous communication system. Symbol timing recovery is indispensable for the receiver to accomplish demodulation and the receiver must make good approximation of channel delay and other nonideal effect introduced by transmitter, channel and receiver.This paper concentrates on all-digital symbol timing recovery algorithm design and its ASIC implementation. Digital TV and DVB-C standard are introduced in the beginning of the paper. All kinds of synchronization techniques and related knowledge are also introduced. According to the requirement of DVB-C, M&M algorithm is selected from the perspective of demodulator architecture and algorithm performance. Considering the new problems in all-digital design, an all-digital symbol timing recovery algorithm is designed, which is simulated and verified using Simulink. The simulation results indicate that the designed algorithm can accomplish the symbol synchronization of DVB-C system. An optimized ASIC design of symbol timing recovery has been introduced in the paper. Compared with other implementation methods, the optimized design saves hardware resources greatly. Circuit is designed using Verilog HDL and it is simulated with Modelsim, VCS. The simulation results prove the designed circuit function well. Timing verification has also been made through analysis and simulation using CHARTERED 0.25μm devices, which proves that the designed circuits meet the timing requirement. Designed circuit also has been compiled using Synopsys Design Compiler and the circuit area is given in the paper.Through the research work done in the paper, symbol timing recovery algorithm compliant to DVB-C is designed, whose ASIC implementation is optimized. The simulation results indicates that both the algorithm and the circuit meet the requirement.