Dvb-c Receiver Symbol Synchronization Interpolation Algorithm Design And Simulation

In recent years, DTV technology is developing rapidly, and the broadcasting system has been transiting into digital mode. DVB-C that is one of the DVB standards has been widely adopted in China at the present time. The efficiency of the symbol timing recovery that is one of the important blocks in a DVB-C digital receiver has a direct effect on the holistic performance. So, the research on the critical algorithms for digitized symbol timing recovery has great value for the design of DVB-C receivers. This dissertation makes a research on the critical technology of symbol timing recovery block in the DVB-C receivers. A class of polynomial basic function is adopted to implement the symbol interpolator, which is the most important part in the symbol timing recovery block. The corresponding function deducing, algorithm developing for the parameter calculation, interpolator performance analysis, optimized structure design and its implementation on FPGA in Verilog are all achieved. Contrasting to the traditional interpolators those have almost the same complexity, the interpolator gained here has greater performance and better flexibility of filtering characteristic control. The work accomplished in this dissertation has great value of implementation and reference for the design of high performance DVB-C receivers.This dissertation includes the contents below:1) Data preparation. Algorithm design and fixed point simulation for base band signal processing and modulation in DVB-C transmitter.2) Research on the theory of all-digitized symbol timing recovery. The formulae are deduced and a recovered symbol clock jitter cancellation method is introduced here as well.3) A class of polynomial basic function is adopted to implement the symbol interpolator, and its uniform polynomial architecture is deduced. Simultaneously two different optimization algorithms are developed to calculate the interpolator parameters. And then a method that generates groups of parameters for the actual application in DVB-C system by grouping the symbol rate is developed.4) The factors those affect the performance of the interpolator are analyzed and simulated. Then a resource reduced structure of the optimized interpolator and its implementation on FPGA in Verilog is given in the end.