Research On Timing Synchronization Based On Symbol-Rate Sampling

The information age has pushed the communication system to develop toward the aim of high speed and low power. Timing synchronization plays an important role in ensuring precise signal decoding performance as it affects the sampling phase and frequency of analog-to-digital convertor (ADC) for incoming signals. The ADC sampling frequency reflects a trade-off between system performance and power consumption, which has become a crucial issue in the design of wireless communication systems. However, traditional methods require a sampling rate greater than the Nyquist rate, which will increase the difficulty for circuit design and result in high power consumption for high speed applications.Based on recent research, this thesis presents a new symbol-rate timing synchronization approach based on adaptive interpolation to reduce the sampling frequency of ADC and power consumption for low-energy high-speed wireless communication systems. Using a principle of maximum absolute-squared sum (MASS), the ADC can select the optimal clock phase provided by a multiple clock generator to sample the incoming signals at the symbol rate. Adaptive interpolation is then introduced to compensate for the performance lose caused by residual timing error due to insufficient amount of clock phases. Both the Least Mean Square (LMS) algorithm and Recursive Least Square (RLS) algorithm can be applied on the adaptive interpolation filter. A theoretical analysis in terms of SIR of both these two adaptive interpolation methods is given.Simulation results and analysis show that the MASS module is able to select the optimal sampling clock, and the sampled signals are significantly recovered after the interpolation process. So the timing synchronization is realized with symbol-rate sampling. Compared with other timing synchronization methods, this method could significantly reduce the power consumption.