The Research And Design Of Pfd Cp For Pll Applied In CMMB Receiver

China Mobile Multimedia Broadcasting (CMMB) is China's own R & D for mobile phone and other mobile terminals for wireless communication systems. It supports multiple sets of television and radio programs and strongly supported by the SARFT. But the R & D of the RF receiver chip in the mobile terminal is still far behind developed countries. So it is of crucial importance to research and design high-performance receiver chip.Synthesizer is an important block in the receiver whose performance is directly related to the accuracy and purity of the local oscillator signals (LO). As the reference frequency of the integer-N Phase-Locked Loop (PLL) must be equal to the channel bandwidth or be one over N of the channel bandwidth and the loop bandwidth of the PLL can't be larger than the one tenth of the reference frequency. In this case, the limitation on the loop bandwidth will impair the settling time of the PLL and make it impossible to serve the requirement of the CMMB protocol. Besides that, there are also some requirements to the resolution of the LO signals in the CMMB protocol. So we select the fractional-N PLL for our design.The main aim of this work is to research the fractional-N PLL in the CMMB application and the realization of the high performance PFD and CP of the PLL.The tasks of this thesis are listed below:At first, this thesis introduces some background of the PLL and compares the differences between the integer-N PLL and the fractional-N PLL. So it is clear to make a selection between these two topologies for a certain receiver. Then some analyses are followed on the operation principle of each blocks and their influence on the PLL output signals. At last, this thesis introduces the design and realization of the PFD and CP in the TSMC0.18umCMOS process. Simulation results are also followed.