Research Of FPGA Implementation ME/MC Based Frame Rate Up Conversion In HDTV

According to plan, our country will close analog television at 2015, and enter the era of digital television. LCD panel is used in a wide range for it's characteristic of small shape, good looking and budget price. Yet, LCD panel encounter the intrinsic drawback of shadow effect and motion blur when the scale become larger. The visual effect decline greatly, especially when LCD displays fast and moving object.To solve this problem, some manufacturers exploit the physical characteristic of LCD panel, try hard to reduce the response time, while some up-convert the frame rate simply with frame repeat method. Another some interpolate black or gray frame to raise the frame rate. All this simple method have no obvious effect on improving visual effect. Recently, the method based on motion estimation and motion compensation(ME/MC) has taken over the hotspot of research area. Using two frame to create one virtual frame, and when this new frame is approach the very state of"middle status", the visual effect will be greatly improved.The research issue is post under this background, and the primary research area is on the ME/MC algorithm which is applicable for frame rate up-conversion, and it's hardware architecture. The hardware architecture here is based on simulated frame rate up-conversion (FRUC) algorithm. To realize the real time processing, we tailor the FRUC algorithm, the overall system reach the balance between real time processing requirement and acceptable subject visual effect. The main contributes are as follows:(1)Improved the motion estimator architecture which was proposed by Lai. The refined architecture preserves features of fast and parallel computing ability,and improved circuits work frequency;(2)Implemented even-odd array motion estimator proposed by Lai and the refined architecture; verified the function and timing of even-odd array motion estimator;(3)Configured MPMC IP core, built the verification environment, verified the function of multi-port read/write simultinously;(4)Proposed the scheme of dividing the whole frame into vertical slice when the frame is being processed. With this technique, the whole numbers and time of accessing external memory drops greatly;(5)Proposed the scheme of adopting multi-level hierarchy memory to buffer the frame data, search window data and block's internal data. The bandwith requirement between ME/MC processing module and external memory is droped when using hierarchy memory;This paper firstly reviewed the basic principle of ME/MC algorithm, and the application of ME/MC in FRUC. Then it illustrated the steps of FRUC algorithm. After that, it proposed the hardware architecture of FRUC algorithm and the design of hierarchy memory, multi-level pipelining, and the main control logic. Chapter 4 reviewed the exsited architectures of full-search motion estimator, then it refined the odd-even architecture proposed by Lai, and finally presented the implementation result. Chapter 5 presented the synthesis and simulation result of multi-port memory controller, and the result of basic debug system. At the end it concluded the paper and forecast the research and development of this area in the future.