Study And Implementation Of Communication Mechanism In Dynamic Reconfigurable Systems

Reconfigurable technique based on FPGA has gradually been the research highlight in the embedded computing research field internationally,with the developing step of the micro-electronics and computer technology. Certain computation-centered tasks are able to be implemented and executed neatly on FPGA, enabling the hardware task the equal concept in the system design as well as the software one, and fostering dramatic changes in the traditional software and hardware cooperation area. The reconfigurable system blended by FPGA and CPU bears the characters as high computing performance, flexibility and wide adaption, which blurs the confinement between the traditional notion of hardware and software, and mixes the high performance of hardware with software, besides the flexibility of software with that of hardware. The communication between those two has been the key point affecting performance in the dynamic reconfigurable system though it has matured that the task management and application technique of software task on the imbedded processor and hardware on FPGA are exclusive to one another. And it is also the high academic research spot even University of California at Berkeley and University of Kansas are involved in.FPGA chip of the virtex 4 series, Xilinx co., and S3C2440 chip, an ARM920T SoC, all together compose of the CPU/FPGA mix system. For the downloader iMPACT, which is provided only for FPGA the pc's LPT by Xilinx, is not suitable for dynamically automatic configuration other than that for static use, during which the whole process should be controlled, separate downloader is consequently indispensible to be studied for FPGA deployment in the SoC system. Thus the bit torrent is loaded by the way of TAG timing sequence via S3C2440 the current I/O simulation, in the partial re-deployable JTAG mode.Under the mode of course granularity coupling the communicating model combining with CPU/FPGA has been designed as for the software and hardware task, of which two are linked that of the General Port of S3C2440 and programmable interface of FPGA, and by way of twice shaking-hands and parallel mode the system fulfilled data communication requirements. Meanwhile a basic communicating protocol and relevant software have been put forward on the basis of dynamic reconfigurable experimental system. The protocol has been proved to meet the hardware and software communication.