Design And Application Agree With Low-rate Data Of High-speed All-digital QPSK Demodulator

All-digital demodulation is a hot field of communications. Our laboratory has researched in this field for quite a long time, and has designed a parallel digital demodulation system at 720MHz sampling frequency for high-speed signals. Due to the constraints of parallel structure, the system does not satisfy users on low-rate data processing. So a new demodulation design on low bit rate signal is needed.In view of the superiority of parallel structures and the excellent performance of high-speed data processing, the structure now in use should be kept and in order to resolve the issue of low bit rate so we can only work on the internal logic of FPGA. In view of this situation, the first key issue to be addressed is that how to convert the data collected by the high-speed ADC chip with relatively high sample points into lower ones which can work in the frequency range of FPGA using a serial structure, thus avoiding the lack of parallel structure.The demodulation system is composed of down-sampling, carrier synchronization and symbol synchronization. The implementation of down-sampling function is divided into two parts: the first part is composed of analog filters preceding to the ADC, I / O interface module in the FPGA and a decimator, which achieves the initial data decimation of IF sampling data; the second part uses the popular structure of CIC filters in recent years, and ISOP filter is used for compensating the defect of pass-band filter CIC. In the serial demodulation structure, carrier synchronization and symbol synchronization use two independent phase-locked loop. The carrier synchronization precedes to the symbol synchronization. Phase detecting algorithm of the carrier synchronization uses the classic COSTAS algorithm, symbol synchronization algorithm uses Gardener algorithm. MATLAB simulation is done to check the function of various parts.VHDL language is used to implement the internal components of FPGA. The down-sampling component includes Integrator, comb filter and decimator. Carrier synchronization includes mixing, time-domain filtering, phasedetecting, loopfilter and NCO. Symbol synchronization includes interpolation, synchronization-error detecting, loopfilter and NCO. the modules used for implementation of the overall function have been simulated and validated. Finally, the entire demodulator is integrated, and performance of which is being tested.