Design And Implementation Of Multi-Rate Digital Signal Processing System Based On FPGA

Multi-rate digital signal processing means decimation or interpolation to change sampling rate of signal. In oil exploration and other fields of digital signal processing, multi-rate digital signal processing technology has been of great concern in order to adapt to different requirements of different sampling rates.Multi-rate digital signal processing system which is designed for the MEMS digital geophone, its core content is to design a multi-rate decimation filter. This design uses Altera’s Cyclone IV series chip EP4CE22F17C6 N as system controller chip and uses Quartus II 11.1 as development tool. The Hardware Description Language Verilog is aimed at completing all of the modules.The hardware circuits are achieved on Altera DE2-115 development system. All of the design results are verified by Quartus II 11.1 embedded logic analyzer Signal Tap II Logic Analyzer and MATLAB. The main work of this paper is as follows:1.We summarized the evaluation of multi-rate decimation filter that designed for MEMS digital geophone through the research on petroleum exploration.2.We determined the structure of the system which is composed of the following 3 parts: ①Multi-rate SINC filter;②Compensation filter;③Equiripple FIR filter.3.We designed the multi-rate SINC filter algorithm for decimation, and optimized decimation parameters and every rank of filter’s parameters.Research shows that: ① Decimation filter designed in this paper can meet the requirements of multi-rate digital signal processing system; ② The optimization design of the filter effectively reduces power consumption In this paper; ③ The FPGA verification results shows that the whole design of the system output is correct, stable performance, fully satisfy the design requirements.