Design And Implementation Of Finite Impulse Response (FIR) Filter

Finite impulse response (FIR) digital filters are widely used as common components in many digital signal processing (DSP) systems. Since the complexity of implementation grows with the filter order, the design of hardware efficient and high throughput FIR filter has become much more demanding. Multiplierless memory-based techniques have been widely used in many applications, in recent years, for their high throughput processing and cost-effective structures. One of the techniques is based on distributed arithmetic (DA) for inner product computation. In the DA-based implementation, the lookup table (LUT) stores all possible values of inner product of the fixed coefficients and the input bit vector. However, since the memory requirement of DA-based implementation increases exponentially with the length of filter order. Therefore, in this paper, we extend further to obtain an efficient design for FIR filter implementation.First, a new DA algorithm for FIR filter implementation is proposed, which is based on the existing offset binary DA algorithm. In conventional DA-based design, the values stored in the LUT are all in two's complement representation. On one hand, it brings benefit to the signal processing, while on the other side, it increases the power consumption of a design. In the new DA-based design, the values stored in the LUT are all nonnegative values. Thus, the values stored in the LUT do not require the two's complement representation, and thereafter the power consumption can be reduced.Systolic designs have an efficient area-time implementation, being supported by its feature such as modularity and regularity of the structure. Besides, they also possess potential to obtain low latency implementation since all the processing elements (PEs) in the systolic array are fully pipelined. The conventional structure of the FIR filter, however, is not the systolic structure, and therefore it needs improvement. While in the existing DA-based systolic structure, it involves too much latency and adders. In this paper, a modified decomposition scheme based on the new DA algorithm is proposed, and then the modified soystolic structure for FIR filter implementation is proposed, as well as the systolic structure based on the existing LUT architectures.Finally, the proposed design along with the existing design are all implemented on an Altera Cyclone-ⅢEP3C240C8 FPGA, and the key measure metrics, namely the logic element (LE), the maximum frequency (Fmax) and the power consumption are obtained. The results show that the proposed design involves significantly less area-time-power-complexity when compared with the existing structures. Then, the influence of the pipeline register on the filter is also discussed. Moreover, the high-speed and medium-speed implementation of the FIR filter is also realized. All the results show the excellent performance of the proposed design. The proposed design can, therefore, being applied in a number of applications.