Design And Implementation Of Partial Response Equalization Technique For High Speed Serial Communication

With the rapid development of information age,people have ever growing requirements on the bandwidths of communication systems.As the main measure to reduce intersymbol interference,equalization technique has been widely used.Among them,partial response equalization technique has been attracting more and more researchers' attention.for its excellent performance in realizing higher rate serial communication.This paper presents a lOGb/s partial response(PR)equalizer in 0.18?m CMOS technology.By incorporating a reshaping filter with high-frequency emphasis and the intrinsic roll-off bandwidth of the channel,a duobinary signal is available at the receiver,reducing the bandwidth requirement of high speed communication.To enhance the performance of the PR equalizer,a two-path oversampling technique is used to cope with the time delay variations due to different process corners.Additionally,adjustable capacitance and load calibration technique are also applied to eliminate the process variations further.The chip area including I/O pads occupies 0.835×0.715mm2 and the power consumption is about 224mW under 1.8V power supply.Post simulation results show that the proposed equalizer works properly at lOGb/s and more than 70%eye opening can be obtained.In order to realize the design of the whole communication link,the pre-coding and decoder structure of duobinary equalization has also been studied.Meanwhile,the design of high-speed comparator has been done.As the bandwidth of the data communication system continues to increase,the proposed partial response equalizer is of great value to reduce the channel bandwidth requirement and improve the signal transmission rate.