Research On LDPC Encoding And Decoding Algorithms Based On IEEE802.16e Protocol

Now, LDPC (Low-Density Parity-Check) codes have been applied to many communication systems for the good performance to near Shannon limit. How to construct utility good codes and to find an efficient decoding algorithm became the research hot spots. With aims of reducing the complexity of encoding and implementing a LDPC decoder with short-decoder-latency, this thesis works at the design of encoding and decoding algorithms of LDPC codes on the base of IEEE802.16e protocol.In the IEEE802.16e system we use QC-LDPC codes to construct the H matrix (parity check matrix) which is component of zero matrixes, identity matrixes and the circle-shift matrixes of identity matrixes. With consideration of the trait of this kind of block matrixes, this thesis designs an encoding algorithms and constructs codes differ in rate and length. For decoding algorithms, after research the traditional decoding algorithms of LDPC codes-LLR BP algorithms, this thesis puts forward an planar modified APP-Based algorithms and with consideration of different performance improved under different SNR, present an alterable factor selecting thought. This planar modified algorithms improved the validity of decoding, ameliorated the status of traditional BP-Based algorithms which are speediness but lacking on performance. For different decoding algorithms, this thesis presidents many simulating results includes of different decoding algorithms with the same code, the same decoding algorithms with codes differ in code length or rate, and also simulations under different modulations. After deeply research on the performance and complexity of these decoding algorithms, there comes the conclusion denotes that this kind LDPC code of encoding and decoding algorithms presented in this thesis is good for the IEEE802.16e system. In the last place, this thesis provided a train of thought on the design of decoder with much consideration of the distinctiveness the H matrix provided, and also analyzed the advantages on saving logical resources and operating speed.