Research And Development Of A Multifunctional IP Core Based On USB 2.0 Protocol

Since the release of USB protocol, USB technology, as a low-cost and short-distance interconnection bus, has been widely used. But, up to now, the research of the USB IP cores having our own intelligent property has been very few, especially the configurable multifunctional USB IP cores, which seems to be empty. Therefore, it is of significance to investigate a configurable multifunctional USB IP core.In this thesis, a multifunctional IP core is designed, which is based on USB 2.0 protocol, configurable and reusable. Modules such as Wishbone controller, DMA controller, FIFO controller, UTMI and ULPI interfaces, SIE serial protocol engine, host controller, device controller and OTG controller are included. It is connected with USB transceiver through the UTMI and ULPI interfaces, and is controlled by the external MCU through Wishbone interconnection bus interface. Its parameters can be configured to achieve one or more USB functions of host, device, hub and OTG. The internal data width, the size of the memory, and the number of endpoints are also can be configured. It is developed with the Top-Down method. In the process of the design, the synthesizability of the codes is totally considered. The combinational logic circuits and sequential logic circuits are designed separately to achieve the best synthesis result.All the codes are described with Verilog HDL. Every module is simulated with Modelsim of Mentor company, and is synthesized and timing-analyzed with Design Compiler of Synopsys company.It is shown that the IP core agrees with the function requirement of the USB 2.0 specification through the functional simulation and the test of the data communication between the host controller and device controller, and that the IP core can satisfy the practical application requirements through the value of the clock slack is 0.47 after the synthesis of the IP core with TSMC 0.18um technical library .