Design And Evaluation Of I/O Library Manufactured By Advanced Process

In today's informational society,integrated circuit has become the basis of the realization of informatization and intelligence in all walks of life.It has played an irreplaceable role in both military and civil affairs.Integrated circuits are always following the Moore's law and develop in the direction of smaller,faster and lower power consumption.There are at least two generations of differences between Chinese mainland IC manufacturing technology and international advanced technology.The development of IC manufacturing technology is undoubtedly the most important thing in the development of China's chip industry.The design of cell library can shorten the design cycle of integrated circuits,because the cell library contains the basic units needed in the design of integrated circuits,and it is an important part of the design of integrated circuits.Due to the reduction of the feature size of current process,the integration of integrated circuits is getting higher and higher.The design of cell library has been widely used in the process of integrated circuit design.Each chip will use input and output unit libraries,but the functions of each set of I/O libraries are different.In this paper,first of all,the various standards of circuit design are defined,and the design of I/O library using domestic advanced FinFET process parameters.The I/O library include the analog I/O cell,digital I/O cell,analog power cell,digital power cell and the power-cut cell.Digital I/O cell includes the input circuit part and the output circuit part.In the input circuit,the signal is de-noised by the schmitt trigger to ensure that the circuit will not be triggered by mistake,and then the 1.8V external signal is converted to 0.8V signal by the structure of voltage-reducing circuit and the pull-up and pull-down resistance.In the output circuit,the signal is converted from 0.8V signal to 1.8V signal through level shift and a series of driving modules.There are four selectable driving strength,12 mA,16mA,20 mA and 24 mA controlled by DS0,DS1.The working frequency of the circuit is 100 MHz.In the design of power cell,power-on detection circuit is added,the generated signal FP is added to the logic operation of the circuit,which can prevent leakage and signal disorder to a certain extent,and save a certain amount of power consumption.In the design of ESD,the RC-clamp structure is used as the current release channel of ESD,using grid metal structure to reduce ESD current density and increase heat dissipation area,so that the circuit can meet the ESD design requirements of HBM 3000 V,CDM 500 V and MM 100 V.This paper covers the whole process of the I/O unit library from the beginning of the circuit design to the layout design and the test results of the chip,because the I/O circuit plays an irreplaceable role in the chip.It is not only the "bridge" of the signal,but also provides ESD protection to the whole chip to a certain extent.The circuit design and the streaming chip test with FinFET process are also the inspection of this new process.Proven.After testing,all the design indicators meet the requirements and meet our design needs,compared with 28 nm,the area of layout is reduced in a certain proportion..