Study On ESD Protection Technology For RFIC

As IC technologies continuously migrate into the VDSM regime, electrostaticdischarge (ESD) protection should be carefully designed for integrated circuit (IC)products to mitigate ESD threaten form natural environment. Chip must have a specialESD protection circuit to reduce the threat, especially for RF IC, ESD protection isfacing greater challenges. It not only needs to meet the ESD protection level, also needto understand the complex interactions between the ESD protection circuitry and coreRF IC circuit being protected. The parasitic capacitors brought by additional ESDdevices will degrade the performance of the core RF circuits, especially as the operatingfrequency increase, the role of this degradation will become more apparent. On onehand, the smaller the area of ESD protection devices, the parasitic capacitance is alsosmaller. On the other hand, ESD devices must be sufficiently large to sustain therequirement of conducting a very large current generated by the ESD event. There is atrade-off between the ESD robustness and its transparency.There are two aspects in this thesis. Design window for ESD protection ispresented according to the failure mechanism of ESD devices. The operation mode ofmost important ESD devices diode, MOSFET, SCR under ESD condition is analyzed,followed by the methods to improve ESD devices’ robustness and adjust the parametersof TLP’s I-V, such as trigger voltage, holding voltage and current, failure current,turn-on resistance, leakage current. In addition this paper proposed a noveldiode-triggered silicon-controlled rectifier (DTSCR) for low-voltage application withextremely narrow ESD design margins.The other hand, studied the full-chip ESD protection, analysis of the static anddynamic Power Clamp design. The other hand, studied the full-chip ESD protection,analysis of the static and dynamic Power Clamp design, proposed a novel ESD powerclamp circuit with enough delay time, the turn-off mechanism, the performance ofavoiding the false triggering.Finally, Analysis LNA with different ESD devices, one with LVTSCR, one withGGNMOS and one without indicate that the standard ESD protection structures degradeLNA performance considerably, particularly for higher frequencies of operation.