Research Of High-performance On-chip Debugging Programmer

In the process of embedded SoC design and development, debugging and testing take the most of the time of the SoC development. How to improve debugging efficency and reduce the system development's time, is related to the products' TTM and the follow-up products development and design. In embedded systems, operating systems and applications are mostly stored in nonvolatile memory, such as Flash, ROM, EPROM, etc. Usually, Flash memory is fast, large capacity, long life, so in SoC system has wide application. In a large number of program debugging tests, due to the multiple programming Flash to load the debugger, so how quickly and flexibly to Flash programming, has become a big issue of the embedded system development. In this paper, we focus on the point of view, and put forward a new JTAG-based method and architecture of Flash fast programming. The gist of the fast programming can be divided into the following steps. Firstly, download the target data to the CPU general-purpose register through the JTAG interface; secondly, control the CPU to run the Flash programming assembler and write the target data to the Flash. This new approach is different from the traditional download process, the CPU can deal with the complex Flash programming quickly, and because the JTAG serial bus is almost used by the target data only, the bandwidth utilization efficiency is very high. The JTAG download speed can be improved significantly. The new architecture is an improved CK510 debug interface that is adopted the technology of break point controlling and memory reusing. It supports the different types of Flash programming through the hardware distinguishes and executes the agent program itself, which has been download to the chip's memory first. In this way, the problem of low bandwidth usage which is caused by the sending of redundancy command through the JTAG interface has been resolved. Simulation results show that the programming speed is 17 times than the traditional methods', and hardware design costs small area resources. It appears both powerful and practical and has some reference value.