Font Size: a A A

Research Of A High-Performance SOC Architecture Used In The Speech Coding And Decoding Algorithm

Posted on:2010-08-10Degree:MasterType:Thesis
Country:ChinaCandidate:L GaoFull Text:PDF
GTID:2178360302959933Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
In order to solve the real-time problems of current speech signal processing in embedded applications, in this paper, we developed a high-bandwidth SOC architecture based on a SPARC V8 compatible RISC processor, which proved to be a good solution to the MELP real-time voice codec algorithm.With the development of modern information industry and silicon technology, in order to be more competitive, the new communications, computers and consumer products must be the rapid increase in functionality, reliability and bandwidth, and the rapid reduction of cost and power consumption. In traditional SOC design methodology, the solution is based on the use of additional silicon chips realized in register transfer level, however, the variability of the market demanding determines this method to be inefficiency. In this paper, the main work and contributions are:1. Introduce a kind of SOC architecture based on the vector coprocessor, this architecture use a 32 bit RISC processor with coprocessor and SIMD instructions to accelerate the application. The principle of the architecture is attaching the hardware logic directly into the CPU pipeline, which is called the tightly-coupled way. In this approach, the hardware logic can be placed entirely under the control of software, so it will be easier for software migration in different algorithms.2. Another contribution is the concept of"shadow register file". This method can doubled the communication bandwidth between processor and coprocessor with small increment in area. It's principle is to broaden the ports of register file with one-write port and two-read port into double the numbers before. These"shadow register file"only replicate part of the core register file, so the increased area in control logic and memory can be very limited.3. The paper also introduce an opensore hardware and software SOC platform. The main work is base on a 32bit RISC processor LEON2, which is a product of Europen Space Agency (ESA). The complete process is based on opensource technologies including the compiler, debugger and the workstations. The good result of this experiment may show the opensource techniques perhaps a new choice for the development of System-on-a-Chip in future.
Keywords/Search Tags:System-on-a-Chip, LEON2, Coprocessor, SIMD, Shadow Registers
PDF Full Text Request
Related items