FPGA Simulation Of LEON2 Applicated To STB

With the rapid development of operation of multimedia and internet, the new type STB can fully use the internet resource in our Country to complete VOD, receipt of digital TV and connection to internet, etc. This type STB have concentrated the compress, moderm, alteration control to a whole without prevenient decode and charge equipment.The text introduce the predominance of LEON2 applicating to the new type STB. The LEON2 developed by Gaisler Research Company and completed in 2003, implements a 32-bit processor IP core conforming to the SPARC V8 architecture. It follow the Leon and ERC32 of ESA .The purpose of LEON2 is balancing the capability and price ,good reliability, portability, scalability, software compatibility, etc. Its hardware resource is configurable, mainly facing embedded system, and can implement through FPGA/CPLD and ASIC technology.LEON2 on-chip resource as follows: separate instruction and data caches; hardware multiplier and divider; interrupt controller; debug support unit with trace buffer; two 24-bit timers; two UARTs; power-down function;watchdog;16-bit I/O port; flexible memory controller; ethernet MAC and PCI interface. The text detailedly introduces the structure and working principle of each model on-chip in LEON2, and the method of simulating the UNIX OS through Cygwin software in Windows OS to configure the models of LEON2. Completing the configure and cut down, test the usable periphery device and interface through the testing bench built by the file appertained LEON2 resource code. At last, translating and editing LEON2 resource code, after analyzing and synthesizing with QUARTUSⅡ6.0, get the top-level model plan of LEON2, and describe each pin of LEON2.Then introduce the construction of LEON2 detailedly, configure the model of LEON2, and build the SOC prototype in FPGA board to develop the hardware and software.