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The System Of High Speed Image Acquisition And Storage Based On FLASH

Posted on:2010-07-05Degree:MasterType:Thesis
Country:ChinaCandidate:R LiuFull Text:PDF
GTID:2178360302959523Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Along with the development of aerial remote sensing technique, the demand of storage speed and capacity for image storage become higher and higher,in addition,the restrict of aseismic condition requires reliability and endurance for shake strictly. SSR (Solid State Recorder) based on semiconductor who without machine parts has been one the mainstream of data strorage in avation and aerospace.FLASH which has the excellence in none volatility, low power consuming, large capacity of per cell is used wider and wider, and become the preferred chip.The target of this thesis is developing the SSR with high speed and large capacity based on FLASH.The system which is used in aviation to get and storage optics remote sensing data as 16MB/S has the characteristic of large capacity,high speed, low power consuming,none volatility,endurance for shake. The system structure will be better expansibility, which can suit for various requirment.The actuality and development trend of home and abroad are analyzed first.Secondly make the holistic scheme based on interface and target.Then divide the system into modules according to design Top-down and modularization, accomplish the design and debug of hardware and software of every modules, show the testing and working results of the system. Lastly, summarize the design and give some expectations of this system.The key techniques involved in this project include: Bring forward Parallel-Bus and Muti-Stage-Flow based on which make the submodule of FLASH to aim at disadvantage of single chip FLASH such as low write speed and little capacity, then the storage speed and capacity of the system can be improved by the FLASH array which is composed with submodule of FLASH, the controlling of FLASH array is realized by FPGA who is programmed by VHDL. Camera Link interface and Ping-Pang-Buffer module are designed to make sure the parallelity and real time of data transfers.The data storaged in the system is transmited to computer via USB2.0, the design of USB2.0 interface is realized by CY7C68013A. For better expansibility, the system uses ARM9 who communicates to PC104 via RS232 as controller to harmonize other modules.The fruit of this project includes: Realize an image gather and storage card which has a capacity of 16GB and a write speed of 16MB/S above. The image which is storaged as RAW format can be transmited to computer via USB2.0, and read by software of StellaImage syllabify. Establish a base for the future storage device with high speed and large capacity.
Keywords/Search Tags:FLASH array, Parallel-Bus, Muti-Stage-Flow, FPGA, USB2.0
PDF Full Text Request
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