Research And Implementation Of High-speed Digital Demultiplexing Arithmetic Based On FPGA

Digital demultiplexing algorithms, which are based on uniform DFT filter bank, are a technology that realizes effectively frequency division demultiplex for multicarrier signal. In recent years, with the development of microelectronic technology and the widespread application of FPGA, the implementation of digital demultiplexing algorithms based on FPGA is a problem with greatest concern. However, it is still a challenging problem to realize it with high speed.Based on in-depth research on the structures of polyphase filters and weighted overlap-adding, the thesis focuses on the FPGA design and hardware implementation of the digital demultiplexing algorithms with the two kinds of structures for a group signal of 32 channels with a 100 megahertz clock rate. The main contributions are as follows:1. The structures of polyphase filters and weighted overlap-adding, which are used to realize digital demutiplexing algorithms, are deeply studied. According to the algorithmic rationale, the floating programs to realize high-speed digital demutiplexing algorithms with the two kinds of structures are performed and the results are verified correctly by MATLAB simulations;2. Two design schemes to realize digital demutiplexing algorithms with the two kinds of structures are proposed, which are compared in every respect. In addition, two fixed-point programs are programmed to verify the source codes;3. Two source codes are programmed with VHDL to realize digital demutiplexing algorithms with the structures of polyphase filters and weighted overlap-adding;4. After finishing the design, functional and timing simulation is performed respectively. Finally, the programs are debugged in hardware platform and the results accurately output.