Design Of High-Speed Fir Digital Filter Based On FPGA

In this thesis, a design of High-speed digital FIR filter based on FPGA had finished, which is low-pass filter, and cut-off frequency of 1M. Pass-band ripple is less than 1 dB, the largest stop-band attenuation is -40 dB, the input and output data are eight binary, and the sampling frequency is 10 M.At first, a brief introduction of the basic principles of digital filter, the property and structure of linear FIR digital filter. In accordance with the performance requirements of the filter, we choice window functions and identify factors. In order to meet the requirements of digital filter, the coefficient of filter had magnified 512 times before using in the design, and used Matlab to prove the principle of digital filter. At the same time outlined EDA technology and FPGA design flow.The second part introduces the FIR digital filter module division and use Verilog language in the Modelsim environment with the functional test. The LUT (Look UP Table) technology is used in the design; the rapid of multiplication is finished by addition cumulative. For the simple coefficient, such as -1,-2 and 4, we could direct shift and negation; the design has been optimized greatly. The redundancy digit is used in the cumulate of sect-product of the design, which is mainly amplification the coefficient based on the design, so in the follow-up cumulation,reduce the sect-product in advance that can lessen the quantity of operation, and the time and resources can be saved.Finally this paper used Modelsim and Quartus II progress a FIR digital filter pre-simulation and post-simulation, and expectations were compared with the simulation results. Then make the simulation of the error analysis. The simulation results show that: 16 bands FIR digital filter design can be achieved for 1 M cutoff frequency of the low-pass filtering, and processing speed of up to 150 M above.