The Design And Implementation Of Receiving Subsystem Of The High-Speed Bit-Error-Rate Instrument

The high-speed Bi t-error-rate testing instrument is designed for high-speed modem in the scheme of "the integrated terminal-processing technology of earth station"system, which data-rate reaches 300Mb/s It not only can evaluate the reliability of this system, but also can be applied to the other high-speed communication system. The mission of the project is to design and realize the receiving subsystem of the Bit-error-rate testing instrumentOn basic of researching the principle of high-speed digital demultiplexer and frame synchronizing, combining the FPGA technology and the ECL circuit design . The high performance Serial-to-Parallel convert chips realizes digital demultiplex and the FPGA realize digital signal processing .this paper introduces the thought of the high-speed circuit design and the basical method of the FPGA design.Finally,Thepaper gives the scheme and hardware realization of the receiving subsystem and points out the side needed to improve in the subsystem.