The Design Of High-Throught LDPC Codec And Its FPGA Implementation

Low-density parity-check codes (LDPC codes) is an important class of channelcodes, which can approach capacity very closely. The implementation of encoder anddecoder has a very high value in engineering area, especially for high throughput over1Gbps.In this thesis, the author combines theory analysis and simulation. The mainfruits are summarized as follows:Introduces the principle of LDPC coding and decoding code; analyzed withdouble diagonal structure of quasi-cyclic LDPC code structure; introduces the principleof bidirectional recursive fast encoder is realized; focus on the methods of improving aparallel decoder throughput rate by using submatrix splitting technique.According to the characteristics of quasi-cyclic double diagonal LDPC checkmatrix, the implementation methods of FPGA LDPC encoder is given, and the mainhardware design and hardware platform measured result is given; coding scheme ofcyclic LDPC code alignment hardware resource and throughput compared to theselection, the decoding algorithm is applicable, and gives the hardware implementationthe design of main structure and decoding throughput...