Font Size: a A A
Keyword [Normalized Min-Sum algorithm]
Result: 1 - 9 | Page: 1 of 1
1. Research And Implement Of Encoding And Decoding Of LDPC Codes Based On IEEE802.16e
2. Study On Quasi-cyclic LDPC Codes And Its FPGA Implementation
3. Based On Ldpc Codes, Dmb-th Codec Research And Design
4. Research On Decoding Performance Of RS Codes Based On Normalized Min-sum And Sphere Decoding
5. Key Technology Research And Simulation Analysis Based On WIMAX Physical Layer
6. Study Of Dual Normalized Min-sum Algorithm And Its Partial Parallel Architecture
7. Design And FPGA Implementation Of Full-Rate High-Speed LDPC Decoder Compatible With DVB-S2X Standard
8. Research And Implementation Of High Coding Gain LDPC Decoding Technology For Wireless Optimal Communication
9. Research And FPGA Implementation Of Layered Partial Parallel LDPC Codec
  <<First  <Prev  Next>  Last>>  Jump to