Temperature Properties Analysis Of Cu/Low-k Interconnects In Deep Sub-micron Integrated Circuit

With the rapid development of the CMOS device technology, the thermal related issues are becoming one of the most challenging problems in deep submicron(DSM) IC design and interconnect delay evaluation is also a crucial concern in DSM IC designs .In this paper, the deep submicron Cu/low-k dielectric multilevel metal interconnects structure is mainly studied. In the multilevel metal interconnects structure, it is commonly used Cu instead of Al as the interconnects metal material to reduce interconnects resistance, and the use of low dielectric constant materials to replace silicon dioxide can effectively reduce the parasitic capacitance of interconnects, thereby to reduce interconnects resistance and interconnect RC delay. However the low thermal conductivity of these materials has further aggravated the temperature of interconnects. In addition, with further reduced of via diameter and increased density of via, via produced a lot of heat and become a very important thermal source, which affects the temperature distribution of the interconnection system. This paper discusses analytical model of multilevel metal interconnects temperature distribution considering via self-heating effect. Though the analytical model, temperature distribution of the single interconnect and multilevel interconnects are established, further more the temperature distribution of via and via self-heating effect to the thermal conductivity are discussed. The paper also proposed a thermal RC network simulation method based on the thermoelectric duality. It can high performance realize fast steady-state and transient conditions temperature analysis of Cu/low-k dielectric interconnects, and proposed optimized methods by inserting dummy via. In a word, after considering these factors the temperature is more closely to the actual temperature distribution of multilevel interconnects. The research results can provide the theoretical foundation and guiding significance for IC designers to design high-performance and high reliability chip.