A Study On Thermal Effects In ULSI Interconnect And Via Systems Considering Via Self-heating

The ever-increasing demand for speed and functionality of Si-based advanced high performance microprocessors, digital signal processing chips, and application specific integrated circuits has resulted in a dramatic reduction of the interconnect metal pitch, more metal levels. Joule heating of the interconnect wires is fast emerging as an urgent issue.Moreover, the continuous scaling of ULSI circuits has resulted in an increase in the aspect ratio of the vias and increases in the current density and associated thermal effects, namely self-heating,which are known to strongly impact reliability of ULSI interconnects. Recently it has been demonstrated that thermal effects will start to dominate interconnect design guidelines for advanced high performance interconnects. Overly pessimistic estimation of the interconnect temperature will lead to overly conservative approach. Hence, accurate estimates of interconnect temperatures are necessary for interconnect performance and reliability assessment in high performance ULSI circuits. The prediction of hot spot temperatures and positions in interconnect and via systems is necessary for ic design to minimize electromigration,stress migration,and high-current filures.This paper presents an analytical thermal model considering via self-heating for estimating the temperature of metal wires and vias and the critical condition for hot spot formation within the vias. Using this model, effects of via and metal line dimensions on both single and parallel lines and the temperatures and positions of hot spot are calculated.It has been shown that via dimensions, metal line dimensions or thermal coupling has significant effects on the temperature distribution of metal wires and vias system. The hot spot locations and the overall temperature field in the interconnect structure are also strongly affected by via and metal line dimensions.