Research And Design Of High Speed DAC Based On ECL In InP-DHBT Technology

With the rapid development of radar system and optic communication, higher speed digital to analog converter (DAC) is in heavy demand, but devices based on silicon can't meet it. Indium phosphor (InP) based double hetero-junction bipolar transistor (DHBT) devices, which is progressively mature, are more attractive in implementation high speed DAC.This thesis presents an overview and study of DAC's architecture and basic principles, InP DHBT's layer design, performance parameters and transistor model. A current steering architecture is chosen to realize DAC in InP DHBT technology.Emitter coupled logic (ECL) was adopted in order to design binary-thermal coder of the DAC. It is worth to note that the trade-off of speed and power dissipation is always the main challenge of ECL circuit design. In order to optimize the circuit, this paper presents an approach of transient analysis of ECL circuit and derives an analytic model of mean propagation delay time. Based on the analytic model, a reasonable comprise has been made between speed and power dissipation.Basic logic cell such as Latch, OR/NOR, Buffer are designed and simulated in this paper. The binary - thermal coder and current switch are designed and simulated respectively. In simulation, the SPS (Sampling Per Second) of this 4-bit DAC using InP- DHBT could reach 33GHz. The differential nonlinearity (DNL) is 0.0087LSB and integral nonlinearity (INL) is 0.0017LSB. The DAC has good monotonic quality.