Optimized Motion Compensation VLSI Implementation For H.264/AVC Decoding

This paper proposed an optimized VLSI implementation of motion compensation in H.264/AVC video decoding. The system architecture, memory organization, as well as pixel calculation are optimized to reduce the computation complexity and memory access. First, self-adaptive pipeline and 4-pixel parallel processing are adopted to enhance the system throughput. Second, we proposed a three-level memory hierarchy and employed VBS method to reduce both memory access power and bandwidth. Finally, the computation complexity and throughput of pixel calculation are carefully optimized. Usually, our design is able to achieve 400cycles/MB performance, with a relatively high throughput and performance. With the same fabrication process, this paper reduced 42% gate count, as well as 35% power reduction, while compared with conventional designs.