VLSI Design And Implementation Of Motion Compensation For MPEG-4 Decoder

MPEG-4 is a multimedia compression standard based on the secondary generation visual coded technology.It has adopted a lot of creative technologies,so the code efficiency and flexibility have been greatly improved than the previously standards.MPEG-4 standard has been applied broadly in the domains of multimedia transmission,storage and searches,with its advantages such as low bit-rate and high compression.Motion compensation is a method which uses the coded picture for reference picture to interpolate the current picture.Lots of new algorithms,such as 4-MV method,directed method,quarter-pixel motion compensation,unrestricted motion compensation and so on,are adopted by the motion compensation tool of MPEG-4. These can enhance the video quality and code efficiency,but increase the difficulty for VLSI design and implementation.The main object of this thesis discusses the VLSI design and implementation of motion compensation for MPEG-4 decoder.The contributions of the essay are summered as followed:(1) The research on the architecture design:With Top-Down method,the motion compensation circuit was divided into four sub-modules:motion vector decoder,address generation module,pixel interpolation module and reconstruction module.Then the four sub-modules were detailed, include the function,the hardware architecture and operation timing.(2) Researches on the optimization design of the key modules:For the motion compensation is the most intensive part of accessing memory and has high throughput,several methods were adopted to improve memory access efficiency,including four pixel interpolator,pixel buffer augmentation,and parallel architecture,which lead to good speedup of motion compensation.(3) Study and optimization of some major algorithms of motion compensation.The implementations of 4-MV method,directed method, quarter-pel motion compensation,and unrestricted motion compensation were discussed in detail.The methods were proposed which can reduce memory consumption for motion vector decoding in 4-MV and unrestricted motion compensation respectively.As for the former,a line buffer is adopted instead of frame buffer,and for the later,a method of coordinate transformation is used.(4) Practices on FPGA prototype implementation and function verification: The function verification of motion compensation module has such characteristics as excessive test suits,sea of test data,and high correlation between sub-modules,so the combination of software based simulation and FPGA prototype based emulation was adopted as the principal verification methodology in our design.The design was described with Verilog HDL.It has been implemented by Field Programmable Gate Array(FPGA).Synthesis was also fulfilled with Synopsys Design compiler,based on SMIC 0.18μm standard cell CMOS technology.Demo experiment with real video stream,shows that the design can meet the real-time decoding requirements of the MPEG-4 simple profile and advanced simple profile.