Study On Inter Prediction Decoder And Its High Performance VLSI Implementation For H.264

With the rapid development in the area of communication technology and computer technology, man is entering into a brand-new multimedia age. As the most important, expressive and complex part in multimedia, digital video plays a more and more important role in information society. Meanwhile, video transmission and processing have become hot focus of study in the field of academe and industry.Joint video team (JVT) has put forward the new video compression standard H.264, which stands for the highest achievement in video coding field. Basing on hybrid coding structure, H.264 improves the key components and gains many new features, such as high-precision, multi-reference frame motion compensation, and efficient entropy coding. H.264 has significant improvements over all previous ones in coding quality and compression ratio. With the same visual perceptive quality, H.264 provides gains in compression efficiency of up to 50% over a wide range of bit rates and video resolutions compared to previous standards, with better network-friendly speciality.Overall, the performance improvements of H.264 are built on the basis of the increasing of complexity and cost of achieving. Among them, inter prediction process is the computing and memory access bottleneck of H.264 decoder, which is much more complicate than ever before. Whether the structure of its VLSI design is efficient directly impacts on their real-time decoding. Basing on studying the inter prediction process, this paper implements it with a VLSI architecture based on three stages pipeline. Simulation results and practical application on H.264 decoder testify that the design can completely meet the real-time decoding requirements.