Study On The High-rate And Mass-capacity Data Recorder Based On FPGA

The paper has analyzed the need for application and the peculiarity of flash, and then puts forward a high-rate and mass-capacity recording design based on flash.Some nonvolatile memory chips are compared in this paper, and then an introduction on how to operate flash is given. In order to improve the speed of writing to and reading from flash, the design makes use of pipelining and parallel extending. The system buffer is an independent FIFO which used to cash the data flow. The system control logic circuit including flash controller, USB controller, FIFO controller and so on are implemented in a FPGA chip. The output interface is USB2.0, The input interface which could be adjustable, now is LVDS for the moment. Based on project experience, the details of state-machine and firmware for USB are illuminated last.The result of the project has provided firm foundation to realize the last standard production and is a nutritious reference.